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| STSR3 SYNCHRONOUS RECTIFIERS SMART DRIVER FOR FLYBACK s s s s s s SUPPLY VOLTAGE RANGE: 4V TO 5.5V TYPICAL PEAK OUTPUT CURRENT: (SOURCE 2A, SINK 3.5A) OPERATING FREQUENCY: 30 TO 750 KHz SMART TURN-OFF ANTICIPATION TIMING AUTOMATIC TURN OFF FOR DUTY CYCLE LESS THAN 14% POSSIBILITY TO OPERATE IN DISCONTINUOUS MODE SO-8 DESCRIPTION STSR3 Smart Driver IC provides a high current outputs to properly drive secondary Power Mosfets used as Synchronous Rectifier in low output voltage, high efficiency Flyback Converters. From a synchronizing clock input, withdrawn on the secondary side of the isolation transformer, the IC generates a driving signal with set dead times with respect to the primary side PWM signal. The IC operation prevents secondary side shoot-through conditions at turn-on of the primary switch providing anticipation in turn-off the output. This smart function is implemented by a fast cycle-after-cycle logic control mechanism, based on a high frequency oscillator synchronized by the clock signal. This anticipation is externally set through external component. A special Inhibit function allows to shut-off the drive output. This feature makes discontinuous conduction mode possible and avoids reverse conduction of the synchronous rectifier. SCHEMATIC DIAGRAM Vcc 2 + BIAS UVLO 5.7V CK 4 PEAK DETECTOR ANTICIPATION SET 3 SETANT + HIGH FREQUENCY OSCILLATOR DIGITAL CONTROL OUTPUT BUFFER + 7 OUTGATE INHIBIT 5 + 25mV 1 N/C 6 8 SGLGND PWRGND June 2003 1/12 STSR3 ABSOLUTE MAXIMUM RATINGS Symbol VCC VINHIBIT VCK PTOT ESD Tstg Top DC Input Voltage Max INHIBIT Voltage (*) Clock Input Voltage Range (*) Continuous Power Dissipation at TA=105C without heatsink Human Body Model Storage Temperature Range Operating Junction Temperature Range Pins 1,2, 4, 5, 6, 7, 8 Pin 3 Parameter Value -0.3 to 6 -0.3 to VCC -0.6 to VCC -0.3 to VCC 270 1 0.9 -55 to +150 -40 to +125 Unit V V V V mW KV KV C C VOUTGATE Max Gate Drive Output Voltage Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. (*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum THERMAL DATA Symbol Rthj-amb Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient (*) SO-8 40 160 Unit C/W C/W (*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 C/W can be obtained improving thermal conductivity of the board ORDERING CODES TYPE STSR3 SO-8 STSR3CD SO-8 (T&R) STSR3CD-TR CONNECTION DIAGRAM (top view) 2/12 STSR3 PIN DESCRIPTION Pin N 1 2 Symbol NC VCC Name and Function No internally connected The supply voltage range from 4.0V to 5.5V allows applications with logic gate threshold mosfets. UVLO feature guarantees proper start-up while it avoids undesirable driving during eventual dropping of the supply voltage. The voltage on this pin sets the anticipation (tANT) in turning off the OUTGATE It is possible to choose among three different anticipation times by discrete partitioning of the supply voltage. This input provides synchronization for IC's operations, being the transitions between the two output conditions based on a positive threshold, equal for the two slopes. A smart internal control logic mechanism using a 15MHz internal oscillator generates proper anticipation timing at the turn-off of each output. This feature allows safe turn-off of Synchronous Rectifier avoiding any eventual shoot-through situation on secondary side at both transitions. Smart clock revelation mechanism makes these operations independent by false triggering pulses generated in light load conditions. Absolute maximum voltage rating of the pin can be exceeded limiting the current flowing into the pin to 10mA max. This input enables OUTGATE to work when its voltage is lower than the negative threshold voltage (VINHIBIT 3 SETANT 4 CK 5 INHIBIT 6 7 SGLGND OUTGATE 8 PWRGND 3/12 STSR3 ELECTRICAL CHARACTERISTICS (VCC=5V, CK= 250kHz, duty-cycle=50%, VINHIBIT =-200mV, TJ =-40 to 125C, unless otherwise specified.) Symbol Parameter Test Conditions Min. Typ. 3.8 3.5 CK=0V CK=0V GATE DRIVER OUTPUTS VOL Output Low Voltage VOH IOUT Output High Voltage Output Source Peak Current Output Sink Peak Current Output Series Source Resistance Output Series Sink Resistance OUTGATE Rise Time OUTGATE Fall Time IZ = 2mA OUTGATE= no load 5.5 3.6 5.8 15 3 0.10 4.70 4.85 2 3.5 0.75 0.5 40 30 50 6 20 5 0.16 V V A Max. 4 Unit V V V mA SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT VCCON Start Threshold VCCOFF VZ ICC Turn OFF Threshold After Start Zener Voltage Unloaded Supply Current OUTGATE= no load IOUTGATE=-200mA IOUTGATE=200mA ROUT IOUTGATE=-200mA IOUTGATE=200mA CLOAD=5nF (Note 1) CLOAD=5nF (Note 1) 1.5 0.8 tR tF tP ns ns ns Clock Propagation Delay to No Load Turn ON of OUTGATE VANT = 0 to 1/3VCC; no load VANT = 1/3VCC to 2/3VCC; no load VANT = 2/3VCC to VCC; no load -0.1 TJ = 25C VINHIBIT = 200mV VINHIBIT = -200mV -30 TURN-OFF ANTICIPATION TIME OUTGATE Turn-off tANT Anticipation Time 75 150 225 0.1 -25 -400 1 250 2.6 13 14 18 20 2.8 ns ISETANT VH IH Leakage Current (Note 2) Threshold Voltage Leakage Current (Note 2) A mV nA A ns V % INHIBIT OUTGATE ENABLE tON(GATE) Minimum OUTGATE On time VINHIBIT = +200mV SYNCHRONIZATION INPUT VCK Reference Voltage TJ = 25C DOFF Duty Cycle Shut Down Duty Cycle Turn ON after Shut Down Note2: Parameter guaranteed by design TJ = 25C TJ = 25C Note1: tR is measured between 10% and 90% of the final voltage; tF is measured between 90% and 10% on the initial voltage 4/12 STSR3 TIMING DIAGRAM APPLICATION INFORMATION: STSR3 IN FLYBACK CONVERTER SECONDARY SIDE Feedback Loop TRANSFORMER Vin Cout MosfetN C1 100nF Vout PWM 7 8 +5V 2 C2 100nF 6 R1 PWRGND OUTGate SGLGND +5V D3 R3 4 R4 Ck Vcc STSR3 INHIBIT SETANT 3 R2 5 R5 D2 D1 +5V option NOTES 1) Ceramic Capacitors C1 and C2 must be placed very close to the IC; 2) R1 and R2 set the anticipation time by partitioning the VCC voltage; 3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range; 4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high; 5) D1 could be necessary to protect INHIBIT pin from negative voltages. 6) D2 could be necessary to protect INHIBIT pin from voltages higher than VCC 7) D3 could be necessary to protect CK pin from voltages higher than VCC. 8) SGLGND layout trace must not include OUTGATE current paths. 9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike. 5/12 STSR3 EXAMPLE OF COMPONENTS SELECTION FOR A FLYBACK CONVERTER Flyback Specification: VIN=36-72V VOUT=3.3V n=Np/Ns=4.5 R3 and R4 are calculated assuring a minimum voltage of 2.8V at Ck pin. At 36V input, the voltage on the secondary winding is 36/4.5=8V. Choosing R3=1.5K, R4 results to be: V CK x R 3 2.8V x 1.5 k R 4 --------------------------------------------------------------- = 1k x ------------------------------------------------------------------------- = 862 8 V - 220A x 1.5 k - 2.8V V IN - I CK ( 2.8 ) x R 3 - V CK R4=1k is chosen. At 72V input the current at Ck pin is calculated as: V IN ( m ax ) - V CC - 0.3 16 - 5 - 0.3 I CK = ---------------------------------------------------- = ----------------------------- = 7.13mA 1.5k R3 This value is below the maximum allowable current flowing into the Ck pin (10mA). If the 10mA value is exceeded an external diode connected to VCC must be added (D3). R1 and R2 values set the anticipation time for OUTGATE. For R1= and R 2=0, tANT=75ns; for R1=R 2=10k, tANT=150ns; for R1=0 and R2=, tANT=225ns. The RC group composed by R5 and the parasitic capacitance of Inhibit pin (typically 5pF) delays the signal on Inhibit comparator. This delay must be lower than 200ns. This condition imposes a maximum value for R5 of about 20k. In general a suggested value for R5 is 10k. At 72V input, the secondary voltage is 16V, so the maximum current flowing into Inhibit pin is 16V/10k=1.6mA which is below the maximum allowable current for the pin (10mA). If the 10mA value is exceeded an external diode (D2) connected to VCC must be added. The maximum negative voltage of -0.6V must be guaranteed for the Inhibit pin. If this negative voltage is exceeded the current must be limited to 50mA. If necessary, a diode (D1) connected to SGLGND can be added to satisfy this specification. 6/12 STSR3 INHIBIT OPERATION OF OUTGATE IN DISCONTINUOUS CONDUCTION MODE INHIBIT OPERATION OF OUTGATE 7/12 STSR3 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25C Figure 1 : Zener Characteristics Figure 4 : Sink-Source ON Resistance vs Temperature Figure 2 : Rise and Fall Time vs Load Capacitor Figure 5 : Clock Threshold Voltage vs Temperature Figure 3 : OUTGATE vs Characteristics Figure 6 : INHIBIT Threshold Voltage vs Temperature 8/12 STSR3 Figure 7 : Supply Current vs Load Capacitor Figure 10 : Duty Cycle Shut Down vs Temperature Figure 8 : Supply Current vs Clock Frequency Figure 11 : Duty Cycle Turn ON After Shut Down vs Temperature Figure 9 : GATE ON Time vs Temperature Figure 12 : Clock Leakage Current vs Clock Voltage 9/12 STSR3 SO-8 MECHANICAL DATA DIM. A A1 A2 B C D E e H h L k ddd 0.1 5.80 0.25 0.40 mm. MIN. 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 8 (max.) 0.04 0.228 0.010 0.016 TYP MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.04 0.043 0.013 0.007 0.189 0.150 0.050 0.244 0.020 0.050 inch TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 0016023/C 10/12 STSR3 Tape & Reel SO-8 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.1 5.5 2.1 3.9 7.9 12.8 20.2 60 22.4 8.5 5.9 2.3 4.1 8.1 0.319 0.216 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.335 0.232 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 11/12 STSR3 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 12/12 |
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